This invention relates to, in general, a III-V semiconductor device, and more particularly, but not limited to, a method of forming a gate structure of a III-V semiconductor device.
A silicon nitride layer and a silicon dioxide layer overlying the silicon nitride layer are typically used to protect the surface of a gallium arsenide semiconductor material. A high power reactive ion etch is used to remove portions of the silicon dioxide layer. As device geometries have shrunk, it has been difficult to maintain a uniform etch of the silicon dioxide layer across a wafer without etching of the underlying silicon nitride layer. This difficulty results in reactive-ion etch induced damage to the gallium arsenide surface. This damage to the gallium arsenide surface results in poor device yield, poor electrical characteristics and performance of the semiconductor device.
Therefore, it would be desirable to have a manufacturable process which allows for the fabrication of gallium arsenide devices free of reactive ion etch induced damage.